The invention relates to a method for fabricating bipolar transistors, as can be used, for example, in radio frequency technology.
Bipolar transistors are the transistors of choice where high switching speeds and/or high output powers are required. Modern bipolar transistors can be operated at frequencies of 50 GHz and above. However, to further increase the switching speed, a number of difficulties still have to be eliminated. Parameters, which limit the frequency, are, in particular, the parasitic capacitance between the collector and the base and the base resistance. It has been possible to reduce both parameters to an ever increasing extent by miniaturization, which has been made possible by methods such as self-aligning of the base and the emitter, LOCOS process step sequences, trench techniques and refined layer techniques, such as selective epitaxy.
A further improvement is provided by bipolar transistors with hetero junctions. Bipolar transistors with hetero junctions are bipolar transistors in which the emitter and the base have different materials or different crystal structures, with different forbidden energy gaps. Suitable selection of the materials used for the base and the emitter allows the energy bands to be matched to one another in such a way that the emitter efficiency and the current amplification of the transistor are very high and the base can be designed to be highly doped and therefore have a good conductivity. A typical representative of this type of bipolar transistors is the Si/SiGe bipolar transistor.
Two embodiments of bipolar transistors of this type are disclosed in U.S. Pat. No. 5,962,879, and are explained below in conjunction with FIGS. 1 and 2.
FIG. 1 shows a cross section through an npn Si/SiGe bipolar transistor with a self-aligned collector-base junction. A buried n+-layer 1-2 was produced by implantation in a p-doped silicon substrate 1-1. The insulating layer 1-3, the polysilicon layer 1-4 and a further insulating layer 1-5 are opened up above the buried n−-layer, in order for a collector 1-6, a base 1-7 and an emitter 1-8 to be grown on there by selective epitaxy, preferably in one process step.
However, while the layers 1-6, 1-7 and 1-8 are being grown on in the region which has been opened up, thin polycrystalline or amorphous silicon layers 1-6-1, 1-7-1 and 1-8-1 are undesirably formed at the side wall of the polysilicon layer 1-4 and, as shown in FIG. 1, can also extend into the region of emitter and collector. These undesired layers may cause a short circuit between the emitter and the collector, to make the transistor unusable.
FIG. 2 shows a further bipolar transistor in accordance with the prior art, in which the above-described drawback of the short circuits being formed is avoided. This is achieved by the polysilicon layer which is responsible for the connection to the base being spatially separated from the base/collector region by a side wall insulation and by the base being produced not by selective deposition, but rather by deposition over the entire surface. Accordingly, no polycrystalline or amorphous silicon layers are formed in the region of the base, so that a short circuit between the emitter and the collector is prevented.
To produce the bipolar transistor shown in FIG. 2, a p-silicon substrate 2-1 with a buried n+-layer 2-2 is provided. An oxide layer 2-3, a p-polysilicon layer 2-4 and a further intermediate oxide (not shown) are applied to the substrate and are opened up by means of a photolithographic process in the region of the active transistor region, all the way down to the oxide layer 2-3. The wall of the region which has been opened up is then covered by a first oxide spacer 2-6 and a second nitride spacer 2-7. Then, the oxide layer 2-3 is also opened up, and the intermediate oxide on the polysilicon layer 2-4 is etched until its thickness is the same as that of the oxide layer 2-3. A first selective epitaxy step then follows, by means of which a monocrystalline silicon layer, which forms the collector 2-8, is grown onto the silicon which has been opened up.
After the collector 2-8 has been produced, the intermediate oxide on the polysilicon layer 24 is etched away. The nitride spacer 2-7 is also etched at the top edge until it reaches the height of the top edge of the polysilicon layer 2-4. Then, the base is grown in monocrystalline form onto the collector, the base in this embodiment comprising the monocrystalline layers of silicon 2-9, undoped SiGe 2-10, p-doped SiGe 2-11 and silicon 2-12 again. However, the layers 2-10, 2-11 and 2-12 may also consist of p-doped silicon which is doped during the growth process. The growth of the base takes place over the entire surface and not selectively, i.e. the layers cover the collector and the polysilicon layer 2-4, by means of which contact is made with the base from the outside.
Then, a metal or silicide layer 2-13 is applied to the silicon layer 2-12, in order to reduce the line resistance to the base, and is patterned together with the base layers 2-9, 2-10, 2-11 and 2-12. This is followed by a further oxide layer 2-14 and the production of an opening with the spacers 2-15. The emitter 2-16 is produced in the opening, i.e. silicon which is doped in situ is grown selectively and in monocrystalline form onto the base. To finish the process, the polysilicon layer 2-17, which makes contact with the emitter, and a passivation layer 2-18 are also applied and the intermetallic connections 2-19 to the base and the collector and the emitter are produced.
However, a drawback of this method is that the collector, the base and the emitter have to be applied in separate epitaxy steps, which is highly complex in terms of process engineering and therefore very expensive. Furthermore, the production of the various spacers 2-6, 2-7 and 2-15 is also very complex.